On a receiving side of a communicating apparatus for carrying out a wireless communication, it is necessary to synchronize a received signal in order to demodulate a signal sent from a transmitting side. In the synchronizing operation, there are required two operations, that is, a synchronous capture for starting a demodulating operation in the case in which an expected signal is received and a synchronous follow-up for monitoring a synchronizing shift in the middle of the demodulation to carry out a phase correction at any time, thereby maintaining a synchronization.
In the latter synchronous follow-up operation, there has been known a method of using a clock reproduced in a synchronous capture to generate a clock having a phase advanced or delayed by one clock for the recovered clock and to carry out a phase correction while shifting the recovered clock every clock.
In the method, however, data which can be selected by the recovered clock are any of data output from an analog-to-digital (A/D) converting circuit. Assuming that n-fold oversampling (n is a natural number) is carried out by the A/D converting circuit, therefore, even if a synchronous follow-up circuit carries out the best operation, a time of approximately T/(2n) at a maximum is shifted from an ideal sample timing by setting T to be a symbol cycle or a chip cycle before and after the phase of the recovered clock is shifted in a phase shift circuit, causing a demodulation error.
In the conventional synchronous follow-up circuit, moreover, a phase shift is detected only when a shift of approximately T/(2n) is generated on the recovered clock. For this reason, there is also a drawback that the phase is shifted for a long period of time.